1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which operates in synchronization with a clock signal, and particularly to a structure of a data reading portion of a clock-synchronous static semiconductor memory device which can operate in a burst mode.
2. Description of the Background Art
For constructing a processing system, which can operate in a fast speed, by fulfilling a gap in operation speed between a main storage device and a microprocessor, such a structure has generally been used in recent years that a cache memory for storing data which are accessed with high frequency is generally arranged between the microprocessor and the main storage device. As such a cache memory, a synchronous burst SRAM (which will be referred to as a "BSRAM" in some cases hereinafter) which operates in synchronization with an external clock signal such as a system clock has been widely used.
FIG. 27 schematically shows a whole structure of a BSRAM in the prior art. The BSRAM shown in FIG. 27 is disclosed, e.g., in IEICE Transaction on Electronics, Vol. E80-C, No. 4, April 1997, pp. 557-565.
In FIG. 27, BSRAM includes a memory array 900 having a plurality of static memory cells arranged in rows and columns, a control circuit 902 which determines states of externally supplied control signals, i.e., an address advance signal /ADV, an address strobe signal /ADS, a write enable signal /WE and an output enable signal /OE at a rising of a clock signal CLK such as a system clock, and generates internal control signals for performing operations in accordance with a result of the determination, an address register 904 which takes in an externally supplied address signal Ade in accordance with an address strobe instructing signal received from control circuit 902, a burst address counter 906 which takes in predetermined bits of external address signal Ade taken into address register 904 and, and changes the address bits thus taken in a predetermined sequence under the control by control circuit 902, and a memory cell select circuit 908 which selects an addressed memory cell in memory array 900 in accordance with internal address signal Adi formed of remaining address signal bits from address register 904 and address bits from burst address counter 906.
Address advance signal /ADV enables the count operation of burst address counter 906. Control circuit 902 changes the count value of burst address counter 906 in synchronization with clock signal CLK when address advance signal /ADV is active (L-level). Burst address counter 906 takes in predetermined bits (column address bits) in address register 904 as a leading address, and performs the count operation in a predetermined sequence for output. Address register 904, which is controlled by control circuit 902, takes in external address signal Ade in synchronization with clock signal CLK when address strobe signal /ADS is active. Write enable signal /WE and output enable signal /OE are signals for enabling write/read of data and output of data, respectively. When signal /OE is at H-level, the BSRAM is in the data output high impedance state.
The BSRAM further includes a read/write circuit 910 which reads and writes data from and into a selected memory cell in memory array 900 under the control by control circuit 902, and an input/output register 912 which transmits data to and from read/write circuit 910 in synchronization with clock signal CLK under the control by control circuit 902. Input/output register 912 includes an input register for data writing and an output register for data output, and performs input and output of data applied thereto in synchronization with clock signal CLK. Read/write circuit 910 includes a main amplifier which is activated in the data read operation as well as a write driver which is activated in the data write operation. An operation of the BSRAM shown in FIG. 27 will be described below with reference to a timing chart of FIG. 28.
In clock cycle #1, address strobe signal /ADS is set to L-level at a rising edge of clock signal CLK. Control circuit 902 applies a strobe instructing signal to address register 904 in response to this activation of address strobe signal /ADS, i.e., to L-level thereof. Address register 904 takes in and latches externally applied address signal Ade(A) in accordance with the address strobe instructing signal from control circuit 902. The address signal taken into address register 904 is output as an internal address signal Adi in clock cycle #1. A predetermined address bit (e.g., the least significant column address signal bit) in the address signal issued from address register 904 is applied to burst address counter 906. Burst address counter 906 does not perform the counting, but operates to take in and output the address signal bit received from address register 904 when address advance signal /ADV is at H-level. In clock cycle #1, therefore, internal address signal Adi is generated in accordance with external address signal Ade.
In clock cycle #2, address strobe signal /ADS and address advance signal /ADV are set to H- and L-levels in synchronization with the rising edge of clock signal CLK, respectively. In this state, address register 904 is in the latching state, and does not take in the externally applied address signal. Meanwhile, burst address counter 906 performs the counting in synchronization with clock signal CLK under the control by control circuit 902, and changes the values of the address signal bits held therein. FIG. 28 represents by way of example an operation in which burst address counter 906 changes the count value by incrementing the count by one, starting from the taken address signal bit.
In this clock cycle #2, memory cell select circuit 908 performs the memory cell selection in accordance with address signal A applied at the rising edge of clock signal CLK and, more specifically, selects an addressed memory cell in memory array 900, and read/write circuit 910 reads data from the selected memory cell. The data read from read/write circuit 910 is latched by input/output register 912.
At next clock cycle #3, data Q(A) which is supplied from input/output register 912 at the rising of clock signal CLK is sampled as output data by a processing device such as an external processor. Inside the BSRAM, the memory selection is performed in accordance with address signal A+1 changed by burst address counter 906, and read/write circuit 910 reads the data of the selected memory cell. When the output data of read/write circuit 910 is made definite, I/O register 912 takes in the definite data. In clock cycle #3, therefore, memory cell data Q(A+1) at this address A+1 is read out, and is made definite at the rising edge of clock signal CLK in clock cycle #4.
In the BSRAM, address advance signal /ADV is set to L-level at each of clock cycles #3 and #4, and address strobe signal /ADS is held at H-level so that burst address counter 906 performs counting under the control by control circuit 902 to increment successively its address to A+2 and A+3. Thereby, the memory selection is performed in accordance with internal address signals A+2 and A+3 at clock cycles #4 and #5, respectively, and the data of the selected memory cells are output from I/O register 912 and are definite at the rising edge of clock signal CLK in clock cycles #5 and #6, respectively.
As shown in FIG. 28, data is read in synchronization with clock signal CLK, and thus the rising edge of clock signal CLK determines the timing of definition of the output data, i.e., data appearing on an output pin. Therefore, it is not necessary to account for a timing margin for definition of the output data, which allows fast reading. Since I/O register 912 is used for reading data in synchronization with clock signal CLK, two clock cycles are required after application of external address signal Ade(A) at clock cycle #1 to output of corresponding memory cell data Q(A). Even in this case, the internal address signal is internally and successively produced every clock cycle for performing the memory cell selection and the reading of memory cell data. Therefore, data can be read every clock cycle after these operations, so that fast access can be performed.
Burst address counter 906 is used and has the count value changed to change the internal address signal. Therefore, it is not necessary to change and set external address signal Ade every clock cycle. Therefore, it is not necessary to drive the address signal line outside the BSRAM every clock cycle, but the operation of internally updating internal address signal Adi is merely performed so that the internal address signal can be rapidly produced every clock cycle. An external address signal line has a large load so that it requires a large current consumption for driving thereof, and its changing speed is limited. Therefore, it is possible to provide a storage device which can achieve fast data transfer.
FIG. 29 schematically shows structures of the array and the data read/write portion in the BSRAM shown in FIG. 27. In FIG. 29, memory array 900 is divided into memory sub-arrays MA#0, MA#1, MA#2 and MA#3 each having a plurality of static memory cells arranged in rows and columns. These memory sub-arrays MA#0-MA#3, of which structures will be described later in detail, include a main word line MWL extending over memory sub-arrays MA#0-MA#3 and local word lines each arranged in only one of the memory sub-arrays and corresponding to the main word line.
Memory select circuit 908 includes a block decoder 908a which decodes a block address signal ADz included in internal address signal Adi, and generates a block select signal designating one of memory sub-arrays MA#0-MA#3, a global row decoder 908b which decodes a row address signal Adx included in internal address signal Adi, and generates a signal designating a row in memory sub-arrays MA#0-MA#3, and a column decoder 908c which is provided commonly to memory sub-arrays MA#0-MA#3 and decodes a column address signal Ady included in internal address signal Adi and generates a column select signal selecting a column in memory sub-arrays MA#0-MA#3.
The signal generated from global row decoder 908b is transmitted onto main word line MWL extending over memory sub-arrays MA#0-MA#3. Block decoder 908a decodes block address signal Adz to drive one of block select signals BS0-BS3 to the active state and thereby designates one of memory sub-arrays MA#0-MA#3. Memory sub-arrays MA#0-MA#3 are selected in accordance with block select signals BS0-BS3, and row selection is performed in the selected memory sub-array in accordance with the row select signal applied from global row decoder 908b. In the nonselected memory sub-arrays, each row is held in the nonselected state.
For memory sub-arrays MA#0-MA#3, there are provided array peripheral circuits 901a-901d, respectively, which select columns and perform writing and reading of internal data into and from selected memory cells. Each of these array peripheral circuits 901a-901d includes a column select gate for selecting a column in accordance with the column select signal from column decoder 908c, and a bit line load circuit for precharging and equalizing each bit line pair (column) in the corresponding one of memory sub-array MA#0-MA#3 to a predetermined potential.
Read/write circuit 910 includes local read/write circuits 910a-910d provided corresponding to memory sub-arrays MA#0-MA#3, respectively. Each of local read/write circuits 910a-910d is activated when the block select signal from block decoder 908a is active, to perform read/write of data to the memory cell on the column selected by the corresponding array peripheral circuit.
A main sense amplifier 910e is coupled commonly to the read circuits in local read/write circuits 910a-910d through a common data bus 911. In the data read operation, main sense amplifier 910e is activated to amplify the data read from the selected memory cell in the selected memory sub-array through the local read/write circuit.
Input/output register 912 includes an output register 912a which takes in the output signal of main sense amplifier 910e in synchronization with the clock signal (not shown), and an input register 912b which takes in the data applied in the data writing in synchronization with the clock signal (not shown), and transmits the same onto common data bus 911 in synchronization with the clock signal. An output buffer 913a buffers the data applied from output register 912a, and produces external read (output) data DQ. Input register 912b receives and stores the buffered external write data through input buffer 913b in the data writing.
The memory sub-array, array peripheral circuit and local read/write circuit form one memory block. The structure shown in FIG. 29 includes four memory blocks MB#0-MB#3, each having the same structure.
FIG. 30 shows more specifically the structure of memory block MB#0 shown in FIG. 29. In FIG. 30, memory block MB#0 includes a plurality of static memory cells MC arranged in rows and columns, a plurality of local word lines LWL00-LWL0m arranged corresponding to the rows of memory cells, respectively, and connected to the memory cells in the corresponding rows, and a plurality of bit line pairs BLP0-BLPn arranged corresponding to the columns of memory cells, respectively, and connected to memory cells MC in the corresponding columns. Local word lines LWL00-LWL0m extend in the row direction only within memory block MB#0, and are driven to the active state in accordance with the word line select signal from a local row decoder 920. Main word lines MWL0-MWL0m for transmitting the row select signal applied from global row decoder 908b are arranged corresponding to local word lines LWL00-LWL0m. Local row decoder 920 drives the local word line corresponding to the selected main word line to the selected state in accordance with block select signal BS0 and the row select signal transmitted onto the main word line from global row decoder 908b. Each of main word lines MWL0-MWLm is arranged commonly to memory blocks MB#0-MB#3 and extends over these memory blocks for transmitting the row select signal to the local row decoders included in memory blocks MB#0-MB#3.
Memory block MB#0 further includes bit line peripheral circuits BPH arranged corresponding to bit line pairs BLP0-BLPn, respectively, and a local data bus LIO0 coupled to the addressed column, i.e., selected column through bit line peripheral circuit BPH. Each bit line peripheral circuit BPH includes an I/O gate for receiving corresponding one of column select signals Y0-Yn from column decoder 908c to electrically connect the bit line pair corresponding to the selected column to local data bus LIO0, and a bit line load circuit for precharging corresponding one of bit line pairs BLP0-BLPn to a predetermined potential during standby. Column select signals Y0-Yn from column decoder 908c are commonly applied to memory blocks MB#0-MB#3.
Memory block MB#0 further includes a local sense amplifier 910aa which is activated, when a local sense amplifier activating signal LSE0 is active, to amplify and transmit the signal potential on local data bus LIO0 onto common read data lines RDL and RDLB included in common data bus 911, and a write driver 910ab which amplifies the signal potential on a write data line WDL included in common data bus 911 to transmit complementary write data onto local data bus LIO0. Local sense amplifier activating signal LSE0 is selectively activated in accordance with block select signal BS0 in data reading operation. Write driver 910ab is activated in accordance with block select signal BS0 in data writing operation, although a path for this is not shown. Memory blocks MB#1-MB#3 likewise include local sense amplifiers and write drivers, respectively. Local data buses independent from each other are likewise arranged for each of these memory blocks. Common data bus 911 is arranged commonly to memory blocks MB#0-MB#3.
Read data bus lines RDL and RDLB are coupled to the main sense amplifier shown in FIG. 29.
Read data bus lines RDL and RDLB are coupled to the main sense amplifier shown in FIG. 29.
FIG. 31 shows a relationship between external address signal Ade and internal address signal Adi. As shown in FIG. 31, external address signal Ade includes a block address signal designating a memory block, a row address signal designating a row of memory cells in the memory block, and a column address signal designating a column in the memory block. These block address signal, row address signal and column address signal are multibit address signals. The least significant two bits of the column address signal are applied to the burst address counter, and the value thereof is successively updated every clock cycle. Therefore, internal address signal Adi designates the same block address and row address as external address signal Ade and, in the first cycle, external address signal Ade and internal address signal Adi designate the same column address.
In the next clock cycle, external address signal Ade and internal address signal Adi differ in value of the column address from each other. In the burst mode of selecting successively the memory cells in accordance with the burst address counter, therefore, different columns in the same memory block and the same memory cell row are successively selected. Description will now be given on an operation of successively reading out memory cell data of 4 bits in memory block MB#0 with reference to FIG. 32.
FIG. 32 shows, by way of example, an operation of successively reading out bit line pairs BLP0-BLP3 in memory block MB#0.
In clock cycle #0, internal address signal Adi is produced in accordance with externally applied address signal Ade, and local word line LWL00 corresponding to the addressed row in memory block MB#0 is driven to the selected state. Responsively, data stored in memory cells MC00-MC0n connected to the selected local word line LWL00 are read onto corresponding bit line pairs BLP0-BLPn, respectively.
In parallel with this operation of selecting the local word line, column decoder 908c performs the column selection, and column select signal Y0 is driven to the selected state. In accordance with column select signal Y0 driven to the selected state, the column select gate, which is included in bit line peripheral circuit BPH provided corresponding to bit line pair BLP0, is turned on to electrically connect bit line pair BLP0 to local data bus LIO0, and data in memory cell MC00 is read onto local data bus line pair LIO0. At this time, block select signal BS0 has already been driven to the H-level and thus the selected state. Then, local sense amplifier activating signal LSE0 is driven to the active state in accordance with activation of block select signal BS0 and local word line LWL00, and local sense amplifier 910aa amplifies and transmits the data on local data bus line LIO0 onto read data bus lines RDL and RDLB.
Then, main sense amplifier activating signal MSE is driven to the active state, and main sense amplifier 910a shown in FIG. 29 is activated so that the data in memory cell MC00 is amplified, and the amplified data is applied to output register 912a (FIG. 29) for storage therein in synchronization with clock signal CLK. The data stored in output register 912a is output via output buffer 913a in synchronization with clock signal CLK.
When a predetermined time elapses in clock cycle #0, local word line LWL00 and column select signal Y0 are both driven to the nonselected state. Block select signal BS0 maintains the selected state.
In next clock cycle #1, the burst address counter performs counting to update the least significant two bits of the column address, and column select signal Y1 from column decoder 908c is driven to the selected state. In this burst mode, the block address and row address do not change, so that local word line LWL00 is driven to the selected state again in clock cycle #1. Block select signal BS0 maintains the selected state and thus H-level for the burst period, i.e., a period for which data is continuously read out in response to one-time external address designation. In this state, data of one of memory cells MC00-MC0n connected to local word line LWL00, more specifically, data of memory cell MC01 connected to bit line pair BLP1 is transmitted onto local data bus line LIO0 through bit line peripheral circuit BPH. Then, local sense amplifier activating signal LSE0 is driven to the active state, and local sense amplifier 910aa is activated. Then, the main sense amplifier is activated, and data of memory cell MC01 is stored in the output register and will be read out through the output buffer in the next cycle.
In subsequent clock cycles #2 and #3, column select signals Y2 and Y3 are successively driven to the selected state, and data of memory cells MC02 and MC03 is successively read out. When expiration of the burst period is designated by a combination of states of external control signals, block select signal BS0 is driven to the nonselected state.
By internally and automatically producing the address signals, the memory cell selection can be performed fast, and fast data transfer can be implemented by reading and outputting data in synchronization with clock signal CLK.
FIG. 33 schematically shows a structure of a portion which generates a timing signal for selecting a row and a column. In FIG. 33, the timing signal generating portion includes a word line activating circuit 925 which is activated in response to activation of chip select signal /CS, to activate a word line activating signal WLE having a predetermined time width in synchronization with clock signal CLK, and a column activating circuit 927 which activates a column select line activating signal CLE having a predetermined time width in accordance with word line activating signal WLE. Word line activating signal WLE generated from word line activating circuit 925 is applied to global row decoder 908b. Column select line activating signal CLE generated from column activating circuit 927 is applied to column decoder 908c. Global row decoder 908b is kept active while word line activating signal WLE is active. Likewise, column decoder 908c is kept active while column select line CLE is active. Block decoder 908a statically decodes the block address signal received from the address register (FIG. 29). The address register resets the contents stored therein each time a new address is taken in response to activation of address strobe signal /ADS. Therefore, block decoder 908a is driven to the inactive or disabled state at the time of taking in the new address.
Word line activating signal WLE determines periods of selection (activation) of word lines MWL and LWL. Column select line activating signal CLE determines the active period of column select signal Y of column decoder 908c. Thus, word line activating signal WLE determines an active period TWLON of local word line LWL00 shown in FIG. 32, and column select line activating signal CLE determines an active period TYON of each of column select signals Y0-Y3.
In the operation of reading data from the memory cell, the local word line is selected, and then data of the selected memory cell is read onto the selected bit line pair and is subsequently transferred onto the local data bus line through the bit line peripheral circuit. Thereafter, the local sense amplifier is activated. In the data write operation, the write driver drives the local data bus line pair to the potential level depending on the write data, and the write data is transmitted onto the bit line pair through the bit line peripheral circuit and is written into the memory cell.
For correctly reading and writing data from and into the memory cell, it is necessary to properly perform the transmission of data between the bit line pair and the memory cell as well as the transmission of data between the bit line pair and the local data bus line pair. Therefore, active period TWLON of the local word line and active period TYON of the column select line must be longer than certain time periods, respectively. Active periods TWLON and TYON can be reduced only to limited extents when a high frequency operation is to be performed by reducing cycle time Tc of clock signal CLK in FIG. 32. Meanwhile, these active and inactive periods TWLON, TWLOFF, TYON and TYOFF satisfy the following relationship: EQU TWLON+TWLOFF.apprxeq.Tc EQU TYON+TYOFF.apprxeq.Tc
When cycle time Tc of clock signal CLK decreases, inactive period TYOFF of column select signal Y decreases relative to active period TYON of column select signal Y because the minimum length of active period TYON is predetermined. During the inactive period of the column select signal, the local data bus lines are precharged and equalized.
FIG. 34 schematically shows a structure of a precharge/equalize portion for the local data bus lines for one memory block. In FIG. 34, the precharge/equalize portion includes an AND circuit 930 receiving column select line activating signal CLE and a block select signal BSi (BS0-BS3), and a precharge/equalize circuit 932 which is activated to precharge and equalize bus lines LIOa and LIOb of local data bus line pair LIO to power supply voltage Vcc level when the output signal of AND circuit 930 is active. The precharge/equalize circuit 932 includes p-channel MOS transistors PTa and PTb provided for local data bus lines LIOa and LIOb, respectively, and receiving on their gates the output signal of AND circuit 930.
In each nonselected memory block, block select signal BSi is at L-level, and the output signal of AND circuit 930 is at L-level. Responsively, precharge/equalize circuit 932 is activated, and local data bus lines LIOa and LIOb are precharged to power supply voltage Vcc level. In the selected memory block, block select signal BSi is at H-level and thus active, and the output signal of AND circuit 930 attains L-level in synchronization with deactivation (L-level) of column select line activating signal CLE. Responsively, precharge/equalize circuit 932 precharges and equalizes local data bus lines LIOa and LIOb to power supply voltage Vcc level.
In the selected memory block, the precharge/equalize period of local data bus lines LIOa and LIOb is equal to inactive period TYOFF of column select line Y. If cycle time Tc of clock signal CLK decreases, and inactive period TYOFF of the column select line decreases, local data bus line pair LIO cannot be precharged and equalized sufficiently. This problem will now be described below with reference to FIG. 35.
FIG. 35 schematically shows change in potential on local data bus line pair LIO. Description will first be given on the case where cycle time Tc of clock signal CLK is long. At time T1, column select signal Y is driven to the active state, and the memory cell data is read onto local data bus line pair LIO after elapsing of time ta. In this state, the local sense amplifier is activated, and the memory cell data is read out. Upon elapsing of active period TYON, column select signal Y is set to the nonselected state, and column select activating signal CLE is deactivated, so that local data bus line pair LIO is precharged and equalized. If cycle time Tc is long, precharge/equalize circuit 932 shown in FIG. 34 restores local data bus line pair LIO to initial power supply voltage Vcc level.
Now, description will be given on the case where cycle time Tc of clock signal CLK is short. At time T2, column select activating signal CLE is activated, and column select signal Y is driven to the selected state. After elapsing of active period TYON, precharge/equalize circuit 932 shown in FIG. 34 equalizes in potential local data bus line pair LIO. If cycle time Tc is short, inactive period TYOFF of column select line and the precharge/equalize period of local data bus line pair LIO are short. Therefore, the precharge/equalize operation is ended at time T3 when the potential on local data bus line pair LIO is not yet restored to the original potential level.
In such an insufficiently precharged and equalized state, a next clock cycle starts, and the data of the selected memory cell is transmitted onto local data bus line pair LIO. It is now assumed that the data read in the cycle starting from time T3 is opposite in logic to the data of the memory cell selected in the cycle starting at time T2. In this case, a sufficiently large potential difference is not yet present on local data bus line pair LIO after time period ta from time T3 when the potential on the local data bus line at a lower potential of local data bus line pair LIO was driven to a high level, and a sufficiently large potential difference will appear after a time period tb from time T3. Therefore, the timing of activating the local sense amplifier must be set at or after elapsing of time period tb after time T3, which impedes fast reading. Due to the signal transmission delay at the main sense amplifier and output register, memory cell data cannot be externally output at the rising edge of clock signal CLK, and the fast reading cannot be performed.
This problem relating to the precharging and equalizing of the data bus line pair likewise arises in common data bus 911. Main sense amplifier 910e operates at each clock cycle, to transmit the data transmitted onto this common data bus to output register 912a (see FIG. 29). If cycle time Tc of clock signal CLK is short and a high frequency operation is to be performed, read data bus lines RDL and RDLB (see FIG. 30) included in common data bus 911 cannot be precharged and equalized sufficiently, and accurate reading or fast reading of the data is impossible. In this case, it is necessary to delay the timing of activating main sense amplifier activating signal MSE shown in FIG. 32. In this case, the timing of definition of the data taken into the output register is delayed so that the read data to be output through the output buffer is not made definite in accordance with the timing of rising of clock signal CLK, and data reading cannot be performed accurately.
More specifically, as shown in FIG. 36, if local sense amplifier activating signal LSE and main sense amplifier activating signal MSE are activated in accordance with delayed timing for reliably performing the precharge/equalize of the internal data bus lines, the timing of definition of the output signal of output register 912a is delayed. Therefore, it is impossible to ensure a sufficiently long setup time (with respect to clock signal CLK) for external read data DQ supplied from output buffer 913a, which in turn buffers the output signal of output register 912a for outputting. This results in a problem that data reading cannot be performed correctly.